
Senior Hardware Verification Engineer F/H
- Sophia-Antipolis, Alpes-Maritimes
- CDI
- Temps-plein
- Define, document, develop, and execute RTL verification tests and coverage for highly parameterized IPs using Python and C++. • Ensure compatibility across industry-standard RTL simulators (e.g., Cadence, Synopsys).
- Maintain and enhance the verification workflow, improve metrics, and increase test automation.
- Develop and implement verification components such as Bus Functional Models (BFMs) and monitors.
- Collaborate closely with cross-functional teams to identify and resolve design and verification issues.
- Minimum of 4 years of professional experience in hardware verification.
- Proficient in RTL design and verification languages: VHDL, Verilog, SystemVerilog, SystemC, Python, and C++.
- Experience with UVM methodology, VIPs, testbenches, and EDA tools.
- Familiarity with formal proof verification techniques is a plus.
- Proficiency in shell scripting and working within Linux environments.
- Good understanding of interconnect technologies and hardware communication protocols (AMBA, OCP, etc.).
- Excellent written and verbal communication skills in both French and English.
- Independent, quality-driven, and highly collaborative team player.
- Master's degree or PhD in Engineering, Computer Science, or a related technical field.