
Junior Hardware Verification Engineer
- Sophia-Antipolis, Alpes-Maritimes
- CDI
- Temps-plein
- Define, document, develop, and execute RTL verification tests and coverage for highly parameterized IPs using Python and C++.
- Ensure compatibility of verification tests with various RTL simulators (Cadence, Synopsys, etc.).
- Maintain and enhance the verification workflow, focusing on improving metrics and increasing automation.
- Develop and implement verification components such as Bus Functional Models (BFMs) and monitors used in test benches.
- Solid understanding of hardware RTL design and verification languages: VHDL, Verilog, SystemC, C++, Python, SystemVerilog.
- Experience in verification methodologies and infrastructure: VIPs, UVM, testbeds, and EDA tools.
- Knowledge of formal proof verification methods is a plus.
- Proficiency in shell scripting.
- Familiarity with interconnect technologies is an advantage.
- Understanding of hardware communication protocols (AMBA, OCP, others).
- Strong written and verbal communication skills in both French and English.
- Curious, autonomous, rigorous, results-driven, with a strong commitment to quality.
- Proven ability to collaborate effectively within a team environment.
- Master's degree or Doctorate in Engineering, Computer Science, or a related field.