SerDes System Architect. Leadership opportunity International applicants welcome

Wibit Consulting & Services

  • Grenoble, Isère
  • 90 000-150 000 €/an
  • CDI
  • Temps-plein
  • Il y a 1 mois
Our client is looking for a Principal Engineer - High-Speed SerDes System Architect to lead next-gen high-speed wireline electrical communication research. Join their High-Speed High-Frequency team within the Board Engineering Lab at their Grenoble Research Center, collaborating closely with HQ technical teams in China to develop 112 Gbit/s+ SerDes systems.📍 Location: Grenoble Research Center (On-site)
💰 Salary: €90,000 - €150,000 per annum
🕒 Employment Type: Permanent🔹 Key Responsibilities✔ High-Speed Research & Innovation - Lead research in high-speed wireline electrical communications, developing new system architectures, designs, models & simulations
✔ Next-Gen SerDes Development - Explore SerDes PHY architectures (signaling, equalization, FEC) for hyperscale data centers & AI infrastructure
✔ Algorithm Development - Optimize complex parameter spaces through advanced algorithm modeling
✔ Industry Collaboration - Work with universities, research institutions & industry partners, participating in IEEE, OIF conferences & standards organizations
✔ Technology Roadmap Definition - Develop long-term high-speed interconnect strategies & project planning
✔ Mentorship & Leadership - Supervise interns, PhD students & engineers, providing technical guidance🔹 What You Bring✅ Master's/PhD in Electrical Engineering, Communication Engineering, Information Technology, or Signal Processing
✅ 10+ years of experience in high-speed wireline electrical communication
✅ Deep expertise in modulation, equalization, synchronization & forward error correction
✅ Proven experience in SerDes architecture (serializer, deserializer) for 56 Gbps, 112 Gbps NRZ & PAM applications
✅ Signal Integrity Expert - Strong background in high-speed link analysis🔹 Preferred Skills➕ Industry Standards - Knowledge of IEEE 802.3, OIF-CEI, InfiniBand, CEI-224G
➕ Advanced Signaling - Understanding of high-order modulation (PAM), single-ended & bidirectional signaling
➕ SerDes Protocols - Experience with DDR, PCIe and other high-speed interfaces
➕ Hardware Design - In-depth knowledge of SerDes, ASICs, DSPs, PCBs, connectors, packaging
➕ Academic & Industry Engagement - Participation in technical conferences & research projects
➕ Innovative Mindset - Passion for technology, problem-solving & high-speed system architecture🔹 Technical Tools & Work🔧 SerDes Modeling & Simulation - Python (preferred), MATLAB, Verilog-A, ADS
🔧 Signal Integrity Tools - ADS, custom models (MATLAB, Python)🎁 Why Join Us?🚀 Work on 112 Gbit/s+ SerDes systems - Cutting-edge technology & high-impact research
🌍 Global Collaboration - Partner with top engineers & researchers worldwide
🎓 Industry & Research Engagement - Work with leading institutions & participate in global conferences
📈 Shape the Future - Define the roadmap for next-generation high-speed communicationsReady to push the limits of high-speed signal integrity? Apply now! 🚀💡#SerDes #HighSpeedDesign #SignalIntegrity #HardwareEngineering #ICTIndustry #HiringNow

Wibit Consulting & Services